Apparatuses and methods consistent with example embodiments relate to an integrated circuit (IC), and more particularly, to an IC including a standard cell including a dummy area.
An IC may be designed based on standard cells. Specifically, standard cells may be arranged based on data defining the IC and routed to generate a layout of the IC. With the miniaturization of semiconductors, a size of patterns in a standard cell and a size of the standard cell may be reduced during a manufacturing process. Thus, the influence of a peripheral structure (i.e., a peripheral layout) of the standard cell upon the standard cell may increase. The influence of the peripheral layout may be referred to as a local layout effect (LLE) or a layout dependent effect (LDE).